1.what are the differences between SIMULATION and SYNTHESIS
Simulation <= verify your design. synthesis <= Check for your timing Simulation is used to verify the functionality of the circuit..
a)Functional Simulation:study of ckt's operation independent of timing parameters and gate delays.
b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.Synthesis:One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology.Basically the synthesis tools convert the design description into equations or components
2.What are the differences between latches & flipflops?There are 2 types of circuits:1. Combinational2. Sequential
Latches and flipflops both come under the category of "sequential circuits".Difference: Latches are level-sensitive, whereas, FF are edge sensitive. By edge sensitive, I mean O/p changes only when there is a clock transition.( from 1 to 0, or from 0 to 1)Example: In a flipflop, inputs have arrived on the input lines at time= 2 seconds. But, output won't change immediately. At time = 3 seconds, clock transition takes place. After that, O/P will change.Flip-flops are of 2 types:1.Positive edge triggered2. negative edge triggered1)fllipflops take twice the nymber of gates as latches2) so automatically delay is more for flipflops3)power consumption is also more
3.What is slack?The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a particular path.Slack may be +ve or -ve.
Simulation <= verify your design. synthesis <= Check for your timing Simulation is used to verify the functionality of the circuit..
a)Functional Simulation:study of ckt's operation independent of timing parameters and gate delays.
b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.Synthesis:One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology.Basically the synthesis tools convert the design description into equations or components
2.What are the differences between latches & flipflops?There are 2 types of circuits:1. Combinational2. Sequential
Latches and flipflops both come under the category of "sequential circuits".Difference: Latches are level-sensitive, whereas, FF are edge sensitive. By edge sensitive, I mean O/p changes only when there is a clock transition.( from 1 to 0, or from 0 to 1)Example: In a flipflop, inputs have arrived on the input lines at time= 2 seconds. But, output won't change immediately. At time = 3 seconds, clock transition takes place. After that, O/P will change.Flip-flops are of 2 types:1.Positive edge triggered2. negative edge triggered1)fllipflops take twice the nymber of gates as latches2) so automatically delay is more for flipflops3)power consumption is also more
3.What is slack?The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a particular path.Slack may be +ve or -ve.
Good questions....
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